The present invention generally relates to testing wafers on which electronic circuits are formed, and more particularly, to a test configuration for testing an electronic circuit.
An important facet of the semiconductor industry resides in being able to provide satisfactorily functioning semiconductor devices. In particular, such semiconductor devices may comprise wafers which are divided into areas which form chips, the shapes and dimensions of which are as close to identical as possible, so as to impart consistent uniform electrical properties thereto.
Generally, semiconductor devices on chips are ordinarily connected to each other with thin strips of metal, referred to in the art as interconnection metallurgy, which in turn contact the wafer surface through a series of pads or bumps. Other connector pad configurations may include an array of electrical contacts or bumps which are distributed over an area; for instance, the widely employed C4 bumps (controlled collapse chip connects). Such bumps or electrical contacts extend above the integrated circuits and have a generally spherical or round cross-sectional configuration.
Although wafers are formed as uniformly as possible through current manufacturing techniques, it is not always feasible that every chip produced is perfect. In order to identify defective chips, electrical tests are performed to facilitate the sorting out of good chips and eliminating defective chips prior to the next step of manufacture.
Ordinarily, active testing of the wafers is performed by a test facility in which the pads or areas on wafers possessing arrays of bumps, such as of C4 bumps, are contacted by an assembly incorporating test probes, in order to successfully probe the integrity of the pads or bumps, it is desirable that an oxide layer, which inevitably forms on the surface of the C4 bumps, be ruptured and penetrated to ensure good electrical contact with the probe while employing only a minimal force to inhibit damaging the pads or bumps.